A well-known type of DRAM employs a deep trench capacitor as shown in "A 0.6 .mu.m.sup.2 256 Mb Trench DRAM Cell With Self-Aligned BuriEd STrap (BEST)" by L. Nesbit, et al in Technical Digest of the International Electron Devices Meeting, Washington D.C. p. 627, 1993.
Deep trench capacitors in the prior art suffer from a number of problems--including complicated process steps that result in a narrow process window, high stress in the adjacent pass transistor, resulting in leakage due to crystal defects, and a high contact resistance interconnecting diffused region between the capacitor and the device.
Conventional deep trench capacitors are made by a process that employs three etch steps on the capacitor polysilicon fill and two collar steps to isolate the buried capacitor plate and to provide a strap connection to bridge the collar at the top of the capacitor and connect to the pass transistor. The process window is very small and high stress and high contact resistance can be caused by an improper recess etch step on the poly liner. Incomplete removal of the films in the recess area will prevent a good storage node contact. During oxidation steps, oxide growing into the seam of the poly trench fill causes stress in the surrounding areas.